CMOS fabrication involves multiple ion implants to introduce dopants into a substrate at desired locations to achieve a specified dopant profile. For example, ion implantation is used for threshold voltage control, channel-stop formation, source/drain formation, and well formation. FIG. 1 illustrates a substrate 100 having a single crystal lattice structure represented by a plurality of nuclei 110. In conventional ion implanting, a dopant, also referred to herein as an ion species, is introduced into substrate 100 to a desired dopant profile 120 depicted by the dotted lines. The desired dopant profile 120 is the desired depth distribution of the dopant as controlled by the specified dose and energy. Generally, an ion implant beam 140 is directed at a surface 105 of substrate 100. When dopant ions 150 encounter nuclei 110, dopant ions 150 are deposited to within the desired dopant profile 120.
Problems arise, however, when dopant ions do not encounter nuclei and channel past the desired dopant profile. FIG. 1 illustrates dopant ions 152 that do not encounter nuclei 110 and channel past the desired dopant profile 120 deeper into substrate 100. A conventional method for reducing channeling is to change the angle of ion implant beam relative to the substrate surface. Angling the incident ion beam reduces channeling, but does not prevent it. Changing the angle of ion implant can also adversely affect the performance of the integrated circuit. Moreover, angling the ion implant may not reduce channeling for a polycrystalline substrate. Another conventional method utilizes a randomizing layer formed of silicon dioxide on the substrate surface to prevent channeling. Deposition and removal of conventional randomizing layers, however, is often incompatible with CMOS fabrication processes. Conventional randomizing layers have poor selectivity, for example, on the order of 1:1, and damage the substrate surface during the removal process.
Thus, there is a need for methods that can reduce channeling during ion implantation that are compatible with CMOS fabrication.